Актуален ли порядок сбоев для атомарных операций x86? ⇐ C++

[Гость]

Consider the definition of

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compare_and_exchange_strong_explicit

:

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_Bool atomic_compare_exchange_strong_explicit( volatile A* obj,
C* expected, C desired,
memory_order succ,
memory_order fail );

I'm confused by the use-case of

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memory_order fail

. Considering x86, it's perfectly clear that

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lock cmpxchg

may fail, but it's also clearly defined that (emphasize mine)

Reads or writes cannot be reordered with I/O instructions, locked
instructions, or serializing instructions

which makes the

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memory_order fail

kind of irrelevant since

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lock

guarantees sequential consistency in any case.
Example:

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#include 

void fail_seqcst(volatile int *p, int *expected, int *desirable){
atomic_compare_exchange_strong_explicit(p, expected, desirable, memory_order_release, memory_order_seq_cst);
}

void fail_relaxed(volatile int *p, int *expected, int *desirable){
atomic_compare_exchange_strong_explicit(p, expected, desirable, memory_order_release, memory_order_relaxed);
}

Compiles to:

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fail_relaxed:
mov       ecx, edx
mov       eax, DWORD PTR [rsi]
lock
cmpxchg   DWORD PTR [rdi], ecx
mov       DWORD PTR [rsi], eax
sete      al
movzx     eax, al
ret

fail_seqcst:
mov       ecx, edx
mov       eax, DWORD PTR [rsi]
lock
cmpxchg   DWORD PTR [rdi], ecx
mov       DWORD PTR [rsi], eax
sete      al
movzx     eax, al
ret

Godbolt
Is there any optimization the compiler may do which would differentiate the code for

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memory_order_relaxed

and

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memory_order_seq_cst

in such case on

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x86

? Or maybe there's an architecture out there which would may make this difference significant?


Источник: https://stackoverflow.com/questions/781 ... -operation