Я новичок в LiteX и пытаюсь создать SoC, объединяющий два ядра RISC-V, используя плату ZCU102. Изначально я концентрируюсь на разработке SoC с одним ядром RISC-V (FireV). Я успешно завершил этапы сборки и загрузки, но не получаю никаких данных от UART. Для тестирования я использую демо-версию и сценарий компоновщика, предоставленный LiteX. Я включил код для создания SoC и скрипт компоновщика. Может ли кто-нибудь подсказать, как решить эту проблему? Будем очень признательны за вашу помощь.
Код создания соцсети
#!/usr/bin/env python3
import argparse
from litex_boards.platforms import xilinx_zcu102
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
import litex.soc.doc as lxsocdoc
import time
from migen import *
from litex.soc.cores.cpu import CPUS
from litex.soc.cores.uart import *
from litex.build.generic_platform import *
from litex.soc.cores.clock import *
from litex.soc.cores.led import LedChaser
from litex.soc.interconnect import csr_bus
from litex.soc.integration.builder import *
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc_core import *
from litex.soc.integration.doc import AutoDoc
from litex.soc.integration.soc import SoCBusHandler, SoCRegion, SoCCSRRegion, SoCError
from litex.build.generic_platform import *
import json
from litex.build.altera.programmer import USBBlaster
from litex.build.io import CRG
import subprocess
# CRG ----------------------------------------------------------------------------------------------
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCMini, AutoDoc):
# Class attributes defining memory mapping for different components.
mem_map = {
"csr": 0x10000000,
"rom": 0x00000000,
"sram": 0x01000000,
"main_ram": 0x01010000,
}
# def __init__(self, platform, platform_name, mux, toolchain="vivado", build_dir='',
def __init__(self, platform, platform_name, toolchain="vivado", build_dir='',
name_1='firev', sram_1_size=0x10000, ram_1_size=0x10000,
rom_1_size=0x10000, bus_data_width=16, sys_clk_freq=int(50e6)):
soc_name_1 = f"{name_1}_soc"
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(sys_clk_freq)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, sys_clk_freq, bus_data_width=bus_data_width,
ident="LiteX standalone SoC generator on {}".format(platform_name))
self.buses = [self.bus]
# Standalone SoC Generation/Re-Integration -------------------------------------------------
contents = [i for i in range(16)]
uart_mux_pads = [platform.request("serial", 0), platform.request("serial", 1)]
# SoC.
# ------------
# Generate standalone SoC.
os.system(
f"litex_soc_gen.py --cpu-type={name_1} --bus-standard=wishbone "
f"--sys-clk-freq=500e6 --name={soc_name_1} "
f"--integrated-rom-size={rom_1_size} "
f"--integrated-main-ram-size={ram_1_size} "
f"--integrated-sram-size={sram_1_size} "
f"--output-dir={os.path.join(build_dir, soc_name_1) if build_dir else ''} "
f"--build 2>errors_core_1.txt")
# Add standalone SoC sources.
platform.add_source(
f"{os.path.join(build_dir, f'{soc_name_1}', 'gateware', f'{soc_name_1}.v') if build_dir else f'build/{soc_name_1}/gateware/{soc_name_1}.v'}")
platform.add_source(
f"{os.path.join(build_dir, f'{soc_name_1}', 'gateware', f'{soc_name_1}_rom.init') if build_dir else f'build/{soc_name_1}/gateware/{soc_name_1}_rom.init'}",
copy=True)
# Add CPU sources.
CPUS[name_1].add_sources(platform, "standard")
# Do standalone SoC instance.
mmap_wb = wishbone.Interface()
self.specials += Instance(f"{soc_name_1}",
# Clk/Rst.
i_clk=ClockSignal("sys"),
i_rst=ResetSignal("sys"),
# UART.
o_uart_tx=uart_mux_pads[0].tx,
i_uart_rx=uart_mux_pads[0].rx,
)
self.bus.add_master(master=mmap_wb)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=xilinx_zcu102.Platform(),
description="LiteX AMP Dual-Core SoC generator on De10Lite")
parser.add_target_argument("--sys-clk-freq", default=500e6, help="System clock frequency.")
parser.add_target_argument("--bus_data_width", default=16, help="Super SoC bus data width.")
parser.add_target_argument('--config_file', help='Configuration file', required=True)
parser.add_target_argument('--config', help='Configuration number', required=True)
parser.add_target_argument("--build_dir", default='', help="Base output directory.")
parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
args = parser.parse_args()
print(parser.soc_argdict)
soc = BaseSoC(
platform_name='zcu102',
platform=parser._platform,
toolchain=parser._toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
bus_data_width=int(args.bus_data_width),
build_dir=args.build_dir,
)
args.output_dir = os.path.join(args.build_dir, soc.platform.name) if args.build_dir else ''
builder = Builder(soc, **parser.builder_argdict)
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
if args.build:
builder.build(**parser.toolchain_argdict, run=args.build_dir)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
lxsocdoc.generate_docs(soc,
f"{os.path.join(args.build_dir, 'documentation') if args.build_dir else 'build/documentation'}",
project_name="soc", author="Nh")
if __name__ == "__main__":
main()
Файл linker.ld:
INCLUDE generated/output_format.ld
ENTRY(_start)
__DYNAMIC = 0;
INCLUDE generated/regions.ld
SECTIONS
{
.dummy :
{
. += 0x3000;
} > sram
.text :
{
_ftext = .;
/* Make sure crt0 files come first, and they, and the isr */
/* don't get disposed of by greedy optimisation */
*crt0*(.text)
KEEP(*crt0*(.text))
KEEP(*(.text.isr))
*(.text .stub .text.* .gnu.linkonce.t.*)
_etext = .;
} > sram
.rodata :
{
. = ALIGN(8);
_frodata = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
*(.got .got.*)
*(.toc .toc.*)
. = ALIGN(8);
_erodata = .;
} > sram
.data :
{
. = ALIGN(8);
_fdata = .;
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
. = ALIGN(8);
_edata = .;
} > sram
.bss :
{
. = ALIGN(8);
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(8);
_ebss = .;
_end = .;
} > sram
}
PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram));
PROVIDE(_fdata_rom = LOADADDR(.data));
PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));
Подробнее здесь: https://stackoverflow.com/questions/782 ... ayed-litex
